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1. general description the lpc2292/2294 microcontrollers are based on a 16/32-bit arm7tdmi-s cpu with real-time emulation and embedded trace support, together with 256 kb of embedded high-speed ?ash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. with their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit adc, 2/4 (lpc2294) advanced can channels, pwm channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. the number of available fast gpios ranges from 76 (with external memory) through 112 (single-chip). with a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. remark: throughout the data sheet, the term lpc2292/2294 will apply to devices with and without the /00 or /01 suf?x. the suf?xes /00 and /01 will be used to differentiate from other devices only when necessary. 2. features 2.1 key features brought by lpc2292/2294/01 devices n fast gpio ports enable port pin toggling up to 3.5 times faster than the original device. they also allow for a port pin to be read at any time regardless of its function. n dedicated result registers for adc(s) reduce interrupt overhead. the adc pads are 5 v tolerant when con?gured for digital i/o function(s). n uart0/1 include fractional baud rate generator, auto-bauding capabilities and handshake ?ow-control fully implemented in hardware. n buffered ssp serial controller supporting spi, 4-wire ssi, and microwire formats. n spi programmable data length and master mode enhancement. n diversi?ed code read protection (crp) enables different security levels to be implemented. this feature is available in lpc2292/2294/00 devices as well. n general purpose timers can operate as external event counters. 2.2 key features common for all devices n 16/32-bit arm7tdmi-s microcontroller in a lqfp144 package. lpc2292/2294 16/32-bit arm microcontrollers; 256 kb isp/iap ?ash with can, 10-bit adc and external memory interface rev. 06 10 december 2007 product data sheet
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 2 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface n 16 kb on-chip static ram and 256 kb on-chip ?ash program memory. 128-bit wide interface/accelerator enables high-speed 60 mhz operation. n in-system programming/in-application programming (isp/iap) via on-chip bootloader software. single ?ash sector or full chip erase in 400 ms and programming of 256 b in 1 ms. n embeddedice-rt and embedded trace interfaces offer real-time debugging with the on-chip realmonitor software as well as high-speed real-time tracing of instruction execution. n two/four (lpc2292/2294) interconnected can interfaces with advanced acceptance ?lters. additional serial interfaces include two uarts (16c550), fast i 2 c-bus (400 kbit/s) and two spis. n eight channel 10-bit adc with conversion time as low as 2.44 m s. n two 32-bit timers (with four capture and four compare channels), pwm unit (six outputs), real-time clock (rtc), and watchdog. n vectored interrupt controller (vic) with con?gurable priorities and vector addresses. n con?gurable external memory interface with up to four banks, each up to 16 mb and 8/16/32-bit data width. n up to 112 general purpose i/o pins (5 v tolerant). up to nine edge/level sensitive external interrupt pins available. n 60 mhz maximum cpu clock available from programmable on-chip pll with settling time of 100 m s. n on-chip crystal oscillator with an operating range of 1 mhz to 30 mhz. n power saving modes include idle and power-down. n processor wake-up from power-down mode via external interrupt. n individual enable/disable of peripheral functions for power optimization. n dual power supply: u cpu operating voltage range of 1.65 v to 1.95 v (1.8 v 0.15 v). u i/o power supply range of 3.0 v to 3.6 v (3.3 v 10 %) with 5 v tolerant i/o pads. 3. ordering information table 1. ordering information type number package name description version lpc2292fbd144 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2292fbd144/00 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2292fbd144/01 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2292fet144/00 tfbga144 plastic thin ?ne-pitch ball grid array package; 144 balls; body 12 12 0.8 mm sot569-1 lpc2292fet144/01 tfbga144 plastic thin ?ne-pitch ball grid array package; 144 balls; body 12 12 0.8 mm sot569-1 lpc2292fet144/g tfbga144 plastic thin ?ne-pitch ball grid array package; 144 balls; body 12 12 0.8 mm sot569-1
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 3 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 3.1 ordering options lpc2294hbd144 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2294hbd144/00 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2294hbd144/01 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 table 1. ordering information continued type number package name description version table 2. ordering options type number flash memory ram can fast gpio/ ssp/ enhanced uart, adc, timer temperature range lpc2292fbd144 256 kb 16 kb 2 channels no - 40 c to +85 c lpc2292fbd144/00 256 kb 16 kb 2 channels no - 40 c to +85 c lpc2292fbd144/01 256 kb 16 kb 2 channels yes - 40 c to +85 c lpc2292fet144/00 256 kb 16 kb 2 channels no - 40 c to +85 c lpc2292fet144/01 256 kb 16 kb 2 channels yes - 40 c to +85 c lpc2292fet144/g 256 kb 16 kb 2 channels no - 40 c to +85 c lpc2294hbd144 256 kb 16 kb 4 channels no - 40 c to +125 c lpc2294hbd144/00 256 kb 16 kb 4 channels no - 40 c to +125 c lpc2294hbd144/01 256 kb 16 kb 4 channels yes - 40 c to +125 c
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 4 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 4. block diagram (1) when test/debug interface is used, gpio/other functions sharing these pins are not available. (2) pins shared with gpio. (3) available in lpc2294 only. (4) ssp interface and high-speed gpio are available on lpc2292/2294/01 only. fig 1. block diagram 002aad184 system clock scl p0[30:0] p2[31:0] p1[31:16], p1[1:0] p3[31:0] sda cs3 to cs0 (2) a23 to a0 (2) bls3 to bls0 (2) oe, we (2) d31 to d0 (2) trst (1) tms (1) tck (1) tdi (1) tdo (1) xtal2 xtal1 sck1 mosi1 miso1 eint3 to eint0 4 cap0 4 cap1 4 mat1 4 mat0 ain3 to ain0 ain7 to ain4 pwm6 to pwm1 ssel1 td2, td1 rd2, rd1 td4, td3 (3) rd4, rd3 (3) txd0, txd1 rxd0, rxd1 dsr1, cts1, dcd1, ri1 amba ahb (advanced high-performance bus) ahb bridge emulation trace module test/debug interface ahb decoder ahb to apb bridge apb divider vectored interrupt controller system functions pll spi1/ssp (4) serial interface i 2 c-bus serial interface uart0/uart1 can watchdog timer external interrupts general purpose i/o pwm0 capture/ compare timer 0/timer 1 a/d converter arm7tdmi-s lpc2292 lpc2294 internal sram controller 16 kb sram arm7 local bus apb (advanced peripheral bus) sck0 mosi0 miso0 ssel0 spi0 serial interface real-time clock system control internal flash controller 256 kb flash rst external memory controller p0, p1, p2, p3 high-speed gpi/o (4) 112 pins total
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 5 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 5. pinning information 5.1 pinning (1) pin con?guration is identical for devices with and without /00 and /01 suf?xes. fig 2. lqfp144 pinning lpc2292fbd lpc2294hbd (1) 108 37 72 144 109 73 1 36 002aad185 (1) pin con?guration is identical for devices with and without /00 and /01 suf?xes. fig 3. tfbga144 pinning 002aad191 transparent top view n m l k j h f d g e c b a 24681012 135791113 ball a1 index area lpc2292fet144 (1)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 6 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface table 3. ball allocation row column 1 2 3 4 5 6 7 8 9 10 11 12 13 a p2[22]/ d22 v dda(1v8) p1[28]/ tdi p2[21]/ d21 p2[18]/ d18 p2[14]/ d14 p1[29]/ tck p2[11]/ d11 p2[10]/ d10 p2[7]/d7 v dd(3v3) v dd(1v8) p2[4]/d4 bv dd(3v3) p1[27]/ tdo xtal2 v ssa(pll) p2[19]/ d19 p2[15]/ d15 p2[12]/ d12 p0[20]/ mat1[3]/ ssel1/ eint3 v dd(3v3) p2[6]/d6 v ss p2[3]/d3 v ss c p0[21]/ pwm5/ cap1[3] v ss xtal1 v ssa reset p2[16]/ d16 p2[13]/ d13 p0[19]/ mat1[2]/ mosi1/ cap1[2] p2[9]/d9 p2[5]/d5 p2[2]/d2 p2[1]/d1 v dd(3v3) d p0[24]/ td2 p1[19]/ trace pkt3 p0[23]/ rd2 p0[22]/ cap0[0]/ mat0[0] p2[20]/ d20 p2[17]/ d17 v ss p0[18]/ cap1[3]/ miso1/ mat1[3] p2[8]/d8 p1[30]/ tms v ss p1[20]/ trace sync p0[17]/ cap1[2]/ sck1/ mat1[2] e p2[25]/ d25 p2[24]/ d24 p2[23] v ss p0[16]/ eint0/ mat0[2]/ cap0[2] p0[15]/ ri1/ eint2 p2[0]/d0 p3[30]/ bls1 f p2[27]/ d27/ boot1 p1[18]/ trace pkt2 v dda(3v3) p2[26]/ d26/ boot0 p3[31]/ bls0 p1[21]/ pipe s tat 0 v dd(3v3) v ss g p2[29]/ d29 p2[28]/ d28 p2[30]/ d30/ain4 p2[31]/ d31/ain5 p0[14]/ dcd1/ eint1 p1[0]/cs0 p3[0]/a0 p1[1]/oe h p0[25]/ rd1 td1 p0[27]/ ain0/ cap0[1]/ mat0[1] p1[17]/ trace pkt1 p0[13]/ dtr1/ mat1[1] p1[22]/ pipe s tat 1 p3[2]/a2 p3[1]/a1 j p0[28]/ ain1/ cap0[2]/ mat0[2] v ss p3[29]/ bls2/ ain6 p3[28]/ bls3/ ain7 p3[3]/a3 p1[23]/ pipe s tat 2 p0[11]/ cts1/ cap1[1] p0[12]/ dsr1/ mat1[0] k p3[27]/ we p3[26]/ cs1 v dd(3v3) p3[22]/ a22 p3[20]/ a20 p0[1]/ rxd0/ pwm3/ eint0 p3[14]/ a14 p1[25]/ extin0 p3[11]/ a11 v dd(3v3) p0[10]/ rts1/ cap1[0] v ss p3[4]/a4
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 7 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface l p0[29]/ ain2/ cap0[3]/ mat0[3] p0[30]/ ain3/ eint3/ cap0[0] p1[16]/ trace pkt0 p0[0]/ txd0/ pwm1 p3[19]/ a19 p0[2]/ scl/ cap0[0] p3[15]/ a15 p0[4]/ sck0/ cap0[1] p3[12]/ a12 v ss p1[24]/ trace clk p0[8]/ txd1/ pwm4 p0[9]/ rxd1/ pwm6/ eint3 m p3[25]/ cs2 p3[24]/ cs3 v dd(3v3) p1[31]/ trst p3[18]/ a18 v dd(3v3) p3[16]/ a16 p0[3]/ sda/ mat0[0]/ eint1 p3[13]/ a13 p3[9]/a9 p0[7]/ ssel0/ pwm2/ eint2 p3[7]/a7 p3[5]/a5 nv dd(1v8) v ss p3[23]/ a23/ xclk p3[21]/ a21 p3[17]/ a17 p1[26]/ rtck v ss v dd(3v3) p0[5]/ miso0/ mat0[1] p3[10]/ a10 p0[6]/ mosi0/ cap0[2] p3[8]/a8 p3[6]/a6 table 3. ball allocation continued row column 1 2 3 4 5 6 7 8 9 10 11 12 13
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 8 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 5.2 pin description table 4. pin description symbol pin (lqfp) pin (tfbga) [1] type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pins 26 and 31 of port 0 are not available. p0[0]/txd0/ pwm1 42 [2] l4 [2] o txd0 transmitter output for uart0. o pwm1 pulse width modulator output 1. p0[1]/rxd0/ pwm3/eint0 49 [4] k6 [4] i rxd0 receiver input for uart0. o pwm3 pulse width modulator output 3. i eint0 external interrupt 0 input p0[2]/scl/ cap0[0] 50 [5] l6 [5] i/o scl i 2 c-bus clock input/output. open-drain output (for i 2 c-bus compliance). i cap0[0] capture input for timer 0, channel 0. p0[3]/sda/ mat0[0]/eint1 58 [5] m8 [5] i/o sda i 2 c-bus data input/output. open-drain output (for i 2 c-bus compliance). o mat0[0] match output for timer 0, channel 0. i eint1 external interrupt 1 input. p0[4]/sck0/ cap0[1] 59 [2] l8 [2] i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0[1] capture input for timer 0, channel 1. p0[5]/miso0/ mat0[1] 61 [2] n9 [2] i/o miso0 master in slave out for spi0. data input to spi master or data output from spi slave. o mat0[1] match output for timer 0, channel 1. p0[6]/mosi0/ cap0[2] 68 [2] n11 [2] i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0[2] capture input for timer 0, channel 2. p0[7]/ssel0/ pwm2/eint2 69 [4] m11 [4] i ssel0 slave select for spi0. selects the spi interface as a slave. o pwm2 pulse width modulator output 2. i eint2 external interrupt 2 input. p0[8]/txd1/ pwm4 75 [2] l12 [2] o txd1 transmitter output for uart1. o pwm4 pulse width modulator output 4. p0[9]/rxd1/ pwm6/eint3 76 [4] l13 [4] i rxd1 receiver input for uart1. o pwm6 pulse width modulator output 6. i eint3 external interrupt 3 input. p0[10]/rts1/ cap1[0] 78 [2] k11 [2] o rts1 request to send output for uart1. i cap1[0] capture input for timer 1, channel 0. p0[11]/cts1/ cap1[1] 83 [2] j12 [2] i cts1 clear to send input for uart1. i cap1[1] capture input for timer 1, channel 1.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 9 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface p0[12]/dsr1/ mat1[0]/rd4 84 [2] j13 [2] i dsr1 data set ready input for uart1. o mat1[0] match output for timer 1, channel 0. i rd4 can4 receiver input (lpc2294 only). p0[13]/dtr1/ mat1[1]/td4 85 [2] h10 [2] o dtr1 data terminal ready output for uart1. o mat1[1] match output for timer 1, channel 1. o td4 can4 transmitter output (lpc2294 only). p0[14]/dcd1/ eint1 92 [4] g10 [4] i dcd1 data carrier detect input for uart1. i eint1 external interrupt 1 input. note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after reset. p0[15]/ri1/ eint2 99 [4] e11 [4] i ri1 ring indicator input for uart1. i eint2 external interrupt 2 input. p0[16]/eint0/ mat0[2]/ cap0[2] 100 [4] e10 [4] i eint0 external interrupt 0 input. o mat0[2] match output for timer 0, channel 2. i cap0[2] capture input for timer 0, channel 2. p0[17]/cap1[2]/ sck1/mat1[2] 101 [2] d13 [2] i cap1[2] capture input for timer 1, channel 2. i/o sck1 serial clock for spi1/ssp [3] . spi clock output from master or input to slave. o mat1[2] match output for timer 1, channel 2. p0[18]/cap1[3]/ miso1/mat1[3] 121 [2] d8 [2] i cap1[3] capture input for timer 1, channel 3. i/o miso1 master in slave out for spi1/ssp [3] . data input to spi master or data output from spi slave. o mat1[3] match output for timer 1, channel 3. p0[19]/mat1[2]/ mosi1/cap1[2] 122 [2] c8 [2] o mat1[2] match output for timer 1, channel 2. i/o mosi1 master out slave in for spi1/ssp [3] . data output from spi master or data input to spi slave. i cap1[2] capture input for timer 1, channel 2. p0[20]/mat1[3]/ ssel1/eint3 123 [4] b8 [4] o mat1[3] match output for timer 1, channel 3. i ssel1 slave select for spi1/ssp [3] . selects the spi interface as a slave. i eint3 external interrupt 3 input. p0[21]/pwm5/ rd3/cap1[3] 4 [2] c1 [2] o pwm5 pulse width modulator output 5. i rd3 can3 receiver input (lpc2294 only). i cap1[3] capture input for timer 1, channel 3. p0[22]/td3/ cap0[0]/ mat0[0] 5 [2] d4 [2] o td3 can3 transmitter output (lpc2294 only). i cap0[0] capture input for timer 0, channel 0. o mat0[0] match output for timer 0, channel 0. p0[23]/rd2 6 [2] d3 [2] i rd2 can2 receiver input. p0[24]/td2 8 [2] d1 [2] o td2 can2 transmitter output. p0[25]/rd1 21 [2] h1 [2] i rd1 can1 receiver input. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 10 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface p0[27]/ain0/ cap0[1]/ mat0[1] 23 [6] h3 [6] i ain0 adc, input 0. this analog input is always connected to its pin. i cap0[1] capture input for timer 0, channel 1. o mat0[1] match output for timer 0, channel 1. p0[28]/ain1/ cap0[2]/ mat0[2] 25 [6] j1 [6] i ain1 adc, input 1. this analog input is always connected to its pin. i cap0[2] capture input for timer 0, channel 2. o mat0[2] match output for timer 0, channel 2. p0[29]/ain2/ cap0[3]/ mat0[3] 32 [6] l1 [6] i ain2 adc, input 2. this analog input is always connected to its pin. i cap0[3] capture input for timer 0, channel 3. o mat0[3] match output for timer 0, channel 3. p0[30]/ain3/ eint3/cap0[0] 33 [6] l2 [6] i ain3 adc, input 3. this analog input is always connected to its pin. i eint3 external interrupt 3 input. i cap0[0] capture input for timer 0, channel 0. p1[0] to p1[31] i/o port 1: port 1 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 2 through 15 of port 1 are not available. p1[0]/cs0 91 [7] g11 [7] o cs0 low-active chip select 0 signal. (bank 0 addresses range 0x8000 0000 to 0x80ff ffff) p1[1]/oe 90 [7] g13 [7] o oe low-active output enable signal. p1[16]/ tracepkt0 34 [7] l3 [7] o tracepkt0 trace packet, bit 0. standard i/o port with internal pull-up. p1[17]/ tracepkt1 24 [7] h4 [7] o tracepkt1 trace packet, bit 1. standard i/o port with internal pull-up. p1[18]/ tracepkt2 15 [7] f2 [7] o tracepkt2 trace packet, bit 2. standard i/o port with internal pull-up. p1[19]/ tracepkt3 7 [7] d2 [7] o tracepkt3 trace packet, bit 3. standard i/o port with internal pull-up. p1[20]/ tracesync 102 [7] d12 [7] o tracesync trace synchronization. standard i/o port with internal pull-up. note: low on this pin while reset is low, enables pins p1[25:16] to operate as trace port after reset. p1[21]/ pipestat0 95 [7] f11 [7] o pipestat0 pipeline status, bit 0. standard i/o port with internal pull-up. p1[22]/ pipestat1 86 [7] h11 [7] o pipestat1 pipeline status, bit 1. standard i/o port with internal pull-up. p1[23]/ pipestat2 82 [7] j11 [7] o pipestat2 pipeline status, bit 2. standard i/o port with internal pull-up. p1[24]/ traceclk 70 [7] l11 [7] o traceclk trace clock. standard i/o port with internal pull-up. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 11 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface p1[25]/extin0 60 [7] k8 [7] i extin0 external trigger input. standard i/o with internal pull-up. p1[26]/rtck 52 [7] n6 [7] i/o rtck returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. note: low on this pin while reset is low, enables pins p1[31:26] to operate as debug port after reset. p1[27]/tdo 144 [7] b2 [7] o tdo test data out for jtag interface. p1[28]/tdi 140 [7] a3 [7] i tdi test data in for jtag interface. p1[29]/tck 126 [7] a7 [7] i tck test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. p1[30]/tms 113 [7] d10 [7] i tms test mode select for jtag interface. p1[31]/ trst 43 [7] m4 [7] i trst test reset for jtag interface. p2[0] to p2[31] i/o port 2 port 2 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. p2[0]/d0 98 [7] e12 [7] i/o d0 external memory data line 0. p2[1]/d1 105 [7] c12 [7] i/o d1 external memory data line 1. p2[2]/d2 106 [7] c11 [7] i/o d2 external memory data line 2. p2[3]/d3 108 [7] b12 [7] i/o d3 external memory data line 3. p2[4]/d4 109 [7] a13 [7] i/o d4 external memory data line 4. p2[5]/d5 114 [7] c10 [7] i/o d5 external memory data line 5. p2[6]/d6 115 [7] b10 [7] i/o d6 external memory data line 6. p2[7]/d7 116 [7] a10 [7] i/o d7 external memory data line 7. p2[8]/d8 117 [7] d9 [7] i/o d8 external memory data line 8. p2[9]/d9 118 [7] c9 [7] i/o d9 external memory data line 9. p2[10]/d10 120 [7] a9 [7] i/o d10 external memory data line 10. p2[11]/d11 124 [7] a8 [7] i/o d11 external memory data line 11. p2[12]/d12 125 [7] b7 [7] i/o d12 external memory data line 12. p2[13]/d13 127 [7] c7 [7] i/o d13 external memory data line 13. p2[14]/d14 129 [7] a6 [7] i/o d14 external memory data line 14. p2[15]/d15 130 [7] b6 [7] i/o d15 external memory data line 15. p2[16]/d16 131 [7] c6 [7] i/o d16 external memory data line 16. p2[17]/d17 132 [7] d6 [7] i/o d17 external memory data line 17. p2[18]/d18 133 [7] a5 [7] i/o d18 external memory data line 18. p2[19]/d19 134 [7] b5 [7] i/o d19 external memory data line 19. p2[20]/d20 136 [7] d5 [7] i/o d20 external memory data line 20. p2[21]/d21 137 [7] a4 [7] i/o d21 external memory data line 21. p2[22]/d22 1 [7] a1 [7] i/o d22 external memory data line 22. p2[23]/d23 10 [7] e3 [7] i/o d23 external memory data line 23. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 12 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface p2[24]/d24 11 [7] e2 [7] i/o d24 external memory data line 24. p2[25]/d25 12 [7] e1 [7] i/o d25 external memory data line 25. p2[26]/d26/ boot0 13 [7] f4 [7] i/o d26 external memory data line 26. i boot0 while reset is low, together with boot1 controls booting and internal operation. internal pull-up ensures high state if pin is left unconnected. p2[27]/d27/ boot1 16 [7] f1 [7] i/o d27 external memory data line 27. i boot1 while reset is low, together with boot0 controls booting and internal operation. internal pull-up ensures high state if pin is left unconnected. boot1:0 = 00 selects 8-bit memory on cs0 for boot. boot1:0 = 01 selects 16-bit memory on cs0 for boot. boot1:0 = 10 selects 32-bit memory on cs0 for boot. boot1:0 = 11 selects internal ?ash memory. p2[28]/d28 17 [7] g2 [7] i/o d28 external memory data line 28. p2[29]/d29 18 [7] g1 [7] i/o d29 external memory data line 29. p2[30]/d30/ ain4 19 [4] g3 [4] i/o d30 external memory data line 30. i ain4 adc, input 4. this analog input is always connected to its pin. p2[31]/d31/ ain5 20 [4] g4 [4] i/o d31 external memory data line 31. i ain5 adc, input 5. this analog input is always connected to its pin. p3[0] to p3[31] i/o port 3 port 3 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. p3[0]/a0 89 [7] g12 [7] o a0 external memory address line 0. p3[1]/a1 88 [7] h13 [7] o a1 external memory address line 1. p3[2]/a2 87 [7] h12 [7] o a2 external memory address line 2. p3[3]/a3 81 [7] j10 [7] o a3 external memory address line 3. p3[4]/a4 80 [7] k13 [7] o a4 external memory address line 4. p3[5]/a5 74 [7] m13 [7] o a5 external memory address line 5. p3[6]/a6 73 [7] n13 [7] o a6 external memory address line 6. p3[7]/a7 72 [7] m12 [7] o a7 external memory address line 7. p3[8]/a8 71 [7] n12 [7] o a8 external memory address line 8. p3[9]/a9 66 [7] m10 [7] o a9 external memory address line 9. p3[10]/a10 65 [7] n10 [7] o a10 external memory address line 10. p3[11]/a11 64 [7] k9 [7] o a11 external memory address line 11. p3[12]/a12 63 [7] l9 [7] o a12 external memory address line 12. p3[13]/a13 62 [7] m9 [7] o a13 external memory address line 13. p3[14]/a14 56 [7] k7 [7] o a14 external memory address line 14. p3[15]/a15 55 [7] l7 [7] o a15 external memory address line 15. p3[16]/a16 53 [7] m7 [7] o a16 external memory address line 16. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 13 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface p3[17]/a17 48 [7] n5 [7] o a17 external memory address line 17. p3[18]/a18 47 [7] m5 [7] o a18 external memory address line 18. p3[19]/a19 46 [7] l5 [7] o a19 external memory address line 19. p3[20]/a20 45 [7] k5 [7] o a20 external memory address line 20. p3[21]/a21 44 [7] n4 [7] o a21 external memory address line 21. p3[22]/a22 41 [7] k4 [7] o a22 external memory address line 22. p3[23]/a23/ xclk 40 [7] n3 [7] i/o a23 external memory address line 23. o xclk clock output. p3[24]/cs3 36 [7] m2 [7] o cs3 low-active chip select 3 signal. (bank 3 addresses range 0x8300 0000 to 0x83ff ffff) p3[25]/cs2 35 [7] m1 [7] o cs2 low-active chip select 2 signal. (bank 2 addresses range 0x8200 0000 to 0x82ff ffff) p3[26]/cs1 30 [7] k2 [7] o cs1 low-active chip select 1 signal. (bank 1 addresses range 0x8100 0000 to 0x81ff ffff) p3[27]/we 29 [7] k1 [7] o we low-active write enable signal. p3[28]/bls3/ ain7 28 [4] j4 [4] o bls3 low-active byte lane select signal (bank 3). i ain7 adc, input 7. this analog input is always connected to its pin. p3[29]/bls2/ ain6 27 [6] j3 [6] o bls2 low-active byte lane select signal (bank 2). i ain6 adc, input 6. this analog input is always connected to its pin. p3[30]/bls1 97 [6] e13 [6] o bls1 low-active byte lane select signal (bank 1). p3[31]/bls0 96 [6] f10 [6] o bls0 low-active byte lane select signal (bank 0). td1 22 [7] h2 [7] o td1: can1 transmitter output. reset 135 [8] c5 [8] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 142 [9] c3 [9] i input to the oscillator circuit and internal clock generator circuits. xtal2 141 [9] b3 [9] o output from the oscillator ampli?er. v ss 3, 9, 26, 38, 54, 67, 79, 93, 103, 107, 111, 128 c2, e4, j2, n2, n7, l10, k12, f13, d11, b13, b11, d7 i ground: 0 v reference. v ssa 139 c4 i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v ssa(pll) 138 b4 i pll analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(1v8) 37, 110 n1, a12 i 1.8 v core power supply: this is the power supply voltage for internal circuitry. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 14 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] lpc2294 only. [2] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [3] ssp interface available on lpc2292/2294/01 only. [4] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. [5] open drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires external pull-up to provide an output functionality. [6] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if con?gured for a digital input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. when con?gured as a n adc input, digital section of the pad is disabled. [7] 5 v tolerant pad with built-in pull-up resistor providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. the pull-up resistors value ranges from 60 k w to 300 k w . [8] 5 v tolerant pad providing digital input (with ttl levels and hysteresis) function only. [9] pad provides special analog functionality. v dda(1v8) 143 a2 i analog 1.8 v core power supply: this is the power supply voltage for internal circuitry. this should be nominally the same voltage as v dd(1v8) but should be isolated to minimize noise and error. v dd(3v3) 2, 31, 39, 51, 57, 77, 94, 104, 112, 119 b1, k3, m3, m6, n8, k10, f12, c13, a11, b9 i 3.3 v pad power supply: this is the power supply voltage for the i/o ports. v dda(3v3) 14 f3 i analog 3.3 v pad power supply: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. table 4. pin description continued symbol pin (lqfp) pin (tfbga) [1] type description
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 15 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6. functional description 6.1 architectural overview the arm7tdmi-s is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on risc principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed cisc. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? a 16-bit thumb set the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. 6.2 on-chip ?ash program memory the lpc2292/2294 incorporate a 256 kb ?ash memory system respectively. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld ?rmware upgrades, etc. when the on-chip bootloader is used, 248 kb of ?ash memory is available for user code. the lpc2292/2294 ?ash memory provides a minimum of 100000 erase/write cycles and 20 years of data retention. on-chip bootloader (as of revision 1.60) provides code read protection (crp) for the lpc2292/2294 on-chip ?ash memory. when the crp is enabled, the jtag debug port, external memory boot and isp commands accessing either the on-chip ram or ?ash memory are disabled. however, the isp ?ash erase command can be executed at any time (no matter whether the crp is on or off). removal of crp is achieved by erasure of full on-chip user ?ash. with the crp off, full access to the chip via the jtag and/or isp is restored.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 16 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.3 on-chip sram on-chip sram may be used for code and/or data storage. the sram may be accessed as 8-bit, 16-bit, and 32-bit. the lpc2292/2294 provide 16 kb of sram. 6.4 memory map the lpc2292/2294 memory maps incorporate several distinct regions, as shown in figure 4 . in addition, the cpu interrupt vectors may be re-mapped to allow them to reside in either ?ash memory (the default) or on-chip static ram. this is described in section 6.19 system control . fig 4. lpc2292/2294 memory map ahb peripherals apb peripherals reserved address space boot block (re-mapped from on-chip flash memory) reserved address space 16 kb on-chip static ram reserved address space 256 kb on-chip flash memory 0xffff ffff 0xf000 0000 0xefff ffff 0xe000 0000 0xc000 0000 0xdfff ffff 0x8000 0000 0x7fff ffff 0x7fff e000 0x7fff dfff 0x4000 4000 0x4000 3fff 0x4000 0000 0x3fff ffff 0x0004 0000 0x0003 ffff 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb 0.0 gb 0x0000 0000 002aaa754
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 17 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.5 interrupt controller the vic accepts all of the interrupt request inputs and categorizes them as fast interrupt request (fiq), vectored interrupt request (irq), and non-vectored irq as de?ned by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are requesting, the vic provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vic register to see what irqs are active. 6.5.1 interrupt sources t ab le 5 lists the interrupt sources for each peripheral function. each peripheral device has one interrupt line connected to the vic, but may have several internal interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. table 5. interrupt sources block flag(s) vic channel # wdt watchdog interrupt (wdint) 0 - reserved for software interrupts only 1 arm core embeddedice, dbgcommrx 2 arm core embeddedice, dbgcommtx 3 timer 0 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 4 timer 1 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 5 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) 6
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 18 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] ssp interface available on lpc2292/2294/01 only. 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. 6.7 external memory controller the external static memory controller is a module which provides an interface between the system bus and external (off-chip) memory devices. it provides support for up to four independently con?gurable memory banks (16 mb each with byte lane enable control) simultaneously. each memory bank is capable of supporting sram, rom, ?ash eprom, burst rom memory, or some external i/o devices. each memory bank may be 8-bit, 16-bit, or 32-bit wide. uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem status interrupt (msi) 7 pwm0 match 0 to 6 (mr0, mr1, mr2, mr3, mr4, mr5, mr6) 8 i2c si (state change) 9 spi0 spif, modf 10 spi1 and ssp [1] spif, modf and txris, rxris, rtris, rorris 11 pll pll lock (plock) 12 rtc rtccif (counter increment), rtcalf (alarm) 13 system control external interrupt 0 (eint0) 14 external interrupt 1 (eint1) 15 external interrupt 2 (eint2) 16 external interrupt 3 (eint3) 17 adc adc 18 can 1 ored can acceptance filter 19 can1 (tx int, rx int) 20, 21 can2 (tx int, rx int) 22, 23 can3 (tx int, rx int) - lpc2294 only 24, 25 can4 (tx int, rx int) - lpc2294 only 26, 27 table 5. interrupt sources continued block flag(s) vic channel #
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 19 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.8 general purpose parallel i/o (gpio) and fast i/o device pins that are not connected to a speci?c peripheral function are controlled by the parallel i/o registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as well as the current state of the port pins. 6.8.1 features ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. 6.8.2 features added with the fast gpio set of registers available on lpc2292/2294/01 only ? fast gpio registers are relocated to the arm local bus for the fastest possible i/o timing, enabling port pin toggling up to 3.5 times faster than earlier lpc2000 devices. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all fast gpio registers are byte addressable. ? entire port value can be written in one instruction. ? ports are accessible via either the legacy group of registers (gpios) or the group of registers providing accelerated port access (fast gpios). 6.9 10-bit adc the lpc2292/2294 each contain a single 10-bit successive approximation adc with four multiplexed channels. 6.9.1 features ? measurement range of 0 v to 3 v. ? capable of performing more than 400000 10-bit samples per second. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. 6.9.2 adc features available in lpc2292/2294/01 only ? every analog input has a dedicated result register to reduce interrupt overhead. ? every analog input can generate an interrupt once the conversion is completed. ? the adc pads are 5 v tolerant when con?gured for digital i/o function(s).
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 20 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.10 can controllers and acceptance ?lter the lpc2292/2294 each contain two/four can controllers. the can is a serial communications protocol which ef?ciently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed networks to low cost multiplex wiring. 6.10.1 features ? data rates up to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can speci?cation 2.0b, iso 11898-1. ? global acceptance filter recognizes 11-bit and 29-bit rx identi?ers for all can buses. ? acceptance filter can provide fullcan-style automatic reception for selected standard identi?ers. 6.11 uarts the lpc2292/2294 each contain two uarts. in addition to standard transmit and receive data lines, the uart1 also provides a full modem control handshake interface. 6.11.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? transmission fifo control enables implementation of software (xon/xoff) ?ow control on both uarts. ? uart1 is equipped with standard modem interface signals. this module also provides full support for hardware ?ow control (auto-cts/rts). 6.11.2 uart features available in lpc2292/2294/01 only compared to previous lpc2000 microcontrollers, uarts in lpc2292/2294/01 introduce a fractional baud rate generator for both uarts, enabling these microcontrollers to achieve standard baud rates such as 115200 bd with any crystal frequency above 2 mhz. in addition, auto-cts/rts ?ow-control functions are fully implemented in hardware. ? fractional baud rate generator enables standard baud rates such as 115200 bd to be achieved with any crystal frequency above 2 mhz. ? auto-bauding. ? auto-cts/rts ?ow-control fully implemented in hardware. 6.12 i 2 c-bus serial i/o controller the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 21 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2292/2294 supports bit rate up to 400 kbit/s (fast i 2 c-bus). 6.12.1 features ? compliant with standard i 2 c-bus interface. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus may be used for test and diagnostic purposes. 6.13 spi serial i/o controller the lpc2292/2294 each contain two spis. the spi is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.13.1 features ? compliant with serial peripheral interface (spi) speci?cation. ? synchronous, serial, full duplex communication. ? combined spi master and slave. ? maximum data bit rate of 1 8 of the input clock rate. 6.13.2 features available in lpc2292/2294/01 only ? eight to 16 bits per frame. ? when the spi interface is used in master mode, the sseln pin is not needed (can be used for a different function).
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 22 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.14 ssp controller (lpc2292/94/01 only) the ssp is a controller capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. data transfers are in principle full duplex, with frames of four to 16 bits of data ?owing from the master to the slave and from the slave to the master. while the ssp and spi1 peripherals share the same physical pins, it is not possible to have both of these two peripherals active at the same time. application can switch on the ?y from spi1 to ssp and back. 6.14.1 features ? compatible with motorolas spi, texas instruments 4-wire ssi, and national semiconductors microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four to 16 bits per frame. 6.15 general purpose timers the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. 6.15.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? timer or external event counter operation ? four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 23 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.15.2 features available in lpc2292/2294/01 only the lpc2292/2294/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the pclk. in this con?guration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. ? timer can count cycles of either the peripheral clock (pclk) or an externally supplied clock. ? when counting cycles of an externally supplied clock, only one of the timers capture inputs can be selected as the timers clock. the rate of such a clock is limited to pclk / 4. duration of high/low levels on the selected cap input cannot be shorter than 1 / (2pclk). 6.16 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 6.16.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(pclk) 256 4) to (t cy(pclk) 2 32 4) in multiples of t cy(pclk) 4. 6.17 real-time clock the real-time clock (rtc) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.17.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra-low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? programmable reference clock divider allows adjustment of the rtc to match various crystal frequencies.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 24 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.18 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc2292/2294. the timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is also based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the mr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 6.18.1 features ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of both types. ? the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 25 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 6.19 system control 6.19.1 crystal oscillator the oscillator supports crystals in the range of 1 mhz to 30 mhz. the oscillator output frequency is called f osc and the arm processor clock frequency is referred to as cclk for purposes of rate equations, etc. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.19.2 pll for additional information. 6.19.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 60 mhz with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle.the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 m s. 6.19.3 reset and wake-up timer reset has two sources on the lpc2292/2294: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch ?lter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the on-chip ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to predetermined values. the wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. this is important at power-on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 26 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface the wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power-on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.19.4 code security (code read protection - crp) this feature of the lpc2292/2294/01 allows the user to enable different levels of security in the system so that access to the on-chip ?ash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a speci?c pattern into a dedicated ?ash location. iap commands are not affected by the crp. there are three levels of the code read protection. crp1 disables access to chip via the jtag and allows partial ?ash update (excluding ?ash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and ?ash ?eld updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full ?ash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disables any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p0[14] pin, too. it is up to the users application to provide (if needed) ?ash update mechanism using iap calls or call reinvoke isp command to enable ?ash update via uart0. remark: devices without a /00 or /01 in the name have only a security level equivalent to crp2 available. 6.19.5 external interrupt inputs the lpc2292/2294 include up to nine edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as four independent interrupt signals. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 6.19.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. vectors may be mapped to the bottom of the on-chip ?ash memory, or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 27 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 6.19.7 power control the lpc2292/2294 support two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. in power-down mode, the oscillator is shut down, and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode, and the logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 6.19.8 apb bus the apb divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). the apb divider serves two purposes. the ?rst is to provide peripherals with the desired pclk via apb bus so that they can operate at the speed chosen for the arm processor. in order to achieve this, the apb bus may be slowed down to 1 2 to 1 4 of the processor clock rate. because the apb bus must work properly at power-up (and its timing cannot be altered if it does not work since the apb divider control registers reside on the apb bus), the default condition at reset is for the apb bus to run at 1 4 of the processor clock rate. the second purpose of the apb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the apb divider is connected to the pll output, the pll remains active (if it was running) during idle mode. 6.20 emulation and debugging the lpc2292/2294 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on port 1. this means that all communication, timer and interface peripherals residing on port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.20.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol converter. embeddedice protocol converter converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communication channel function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the debug communication channel is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the debug
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 28 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface communication channel allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic. the jtag clock (tck) must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. 6.20.2 embedded trace since the lpc2292/2294 have signi?cant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. the embedded trace macrocell (etm) provides real-time trace capability for deeply embedded processor cores. it outputs information about processor execution to the trace port. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer must capture the trace information under software debugger control. instruction trace (or pc trace) shows the ?ow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is signi?cantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code cannot be traced because of this restriction. 6.20.3 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the debug communications channel (dcc), which is present in the embeddedice logic. the lpc2292/2294 contain a speci?c con?guration of realmonitor software programmed into the on-chip ?ash memory.
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 29 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 7. limiting values [1] the following applies to t ab le 6 : a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] internal rail. [3] external rail. [4] including voltage on outputs in 3-state mode. [5] only valid when the v dd(3v3) supply voltage is present. [6] not to exceed 4.6 v. [7] per supply pin. [8] the peak current is limited to 25 times the corresponding maximum current. [9] per ground pin. [10] dependent on package type. [11] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(1v8) supply voltage (1.8 v) [2] - 0.5 +2.5 v v dd(3v3) supply voltage (3.3 v) [3] - 0.5 +3.6 v v dda(3v3) analog supply voltage (3.3 v) - 0.5 +4.6 v v ia analog input voltage - 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins [4] [5] - 0.5 +6.0 v other i/o pins [4] [6] - 0.5 v dd(3v3) + 0.5 v i dd supply current [7] [8] - 100 ma i ss ground current [8] [9] - 100 ma t j junction temperature - 150 c t stg storage temperature [10] - 65 +150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model [11] all pins - 2000 +2000 v
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 30 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 8. static characteristics table 7. static characteristics t amb = - 40 c to +125 c, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd(1v8) supply voltage (1.8 v) [2] 1.65 1.8 1.95 v v dd(3v3) supply voltage (3.3 v) [3] 3.0 3.3 3.6 v v dda(3v3) analog supply voltage (3.3 v) 2.5 3.3 3.6 v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd(3v3) ; no pull-down - - 3 m a i oz off-state output current v o =0v, v o =v dd(3v3) ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 c 100 - - ma v i input voltage [4] [5] [6] 0 - 5.5 v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = - 4 ma [7] v dd(3v3) - 0.4 - - v v ol low-level output voltage i ol = 4 ma [7] - - 0.4 v i oh high-level output current v oh =v dd(3v3) - 0.4 v [7] - 4 --ma i ol low-level output current v ol = 0.4 v [7] 4 --ma i ohs high-level short-circuit output current v oh =0v [8] -- - 45 ma i ols low-level short-circuit output current v ol =v dd(3v3) [8] - - 50 ma i pd pull-down current v i =5v [9] 10 50 150 m a i pu pull-up current v i =0v [10] - 15 - 50 - 85 m a v dd(3v3) < v i < 5 v [9] 000 m a power consumption lpc2292, lpc2292/00, lpc2294, lpc2294/00 i dd(act) active mode supply current v dd(1v8) = 1.8 v; cclk = 60 mhz; t amb =25 c; code while(1){} executed from ?ash; all peripherals enabled via pconp [11] register but not con?gured to run -50-ma
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 31 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] typical ratings are not guaranteed. the values listed are at room temperature (+25 c), nominal supply voltages. [2] internal rail. [3] external rail. [4] including voltage on outputs in 3-state mode. [5] v dd(3v3) supply voltages must be present. [6] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. i dd(pd) power-down mode supply current v dd(1v8) = 1.8 v; t amb =25 c -10- m a v dd(1v8) = 1.8 v; t amb =85 c - 110 500 m a v dd(1v8) = 1.8 v; t amb = 125 c - 300 1000 m a power consumption lpc2292/01 and lpc2294/01 i dd(act) active mode supply current v dd(1v8) = 1.8 v; cclk = 60 mhz; t amb =25 c; code while(1){} executed from ?ash; all peripherals enabled via pconp [11] register but not con?gured to run -45-ma i dd(idle) idle mode supply current v dd(1v8) = 1.8 v; cclk = 60 mhz; t amb =25 c; executed from ?ash; all peripherals enabled via pconp [11] register but not con?gured to run - 11.5 - ma i dd(pd) power-down mode supply current v dd(1v8) = 1.8 v; t amb =25 c -10- m a v dd(1v8) = 1.8 v; t amb =85 c - - 180 m a v dd(1v8) = 1.8 v; t amb = 125 c - - 430 m a i 2 c-bus pins v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.5v dd(3v3) -v v ol low-level output voltage i ols = 3 ma [7] - - 0.4 v i li input leakage current v i =v dd(3v3) [12] -24 m a v i =5v - 10 22 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v table 7. static characteristics continued t amb = - 40 c to +125 c, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 32 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [7] accounts for 100 mv voltage drop in all supply lines. [8] only allowed for a short time period. [9] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [10] applies to p1[25:16]. [11] see the lpc2119/2129/2194/2292/2294 user manual . [12] to v ss .
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 33 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] conditions: v ssa =0v, v dda = 3.3 v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 5 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 5 . [5] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 5 . [6] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 5 . [7] the absolute voltage error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 5 . table 8. adc static characteristics v dda = 2.5 v to 3.6 v; t amb = - 40 c to +125 c unless otherwise speci?ed. adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance --1pf e d differential linearity error [1] [2] [3] -- 1 lsb e l(adj) integral non-linearity [1] [4] -- 2 lsb e o offset error [1] [5] -- 3 lsb e g gain error [1] [6] -- 0.5 % e t absolute error [1] [7] -- 4 lsb
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 34 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 5. adc characteristics 002aaa668 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 35 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 8.1 power consumption measurements for lpc2292/01 and lpc2294/01 the power consumption measurements represent typical values for the given conditions. the peripherals were enabled through the pconp register, but for these measurements, the peripherals were not con?gured to run. peripherals were disabled through the pconp register. for a description of the pconp register bits, refer to the lpc2119/2129/2194/2292/2294 user manual . test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb =25 c; core voltage 1.8 v. fig 6. typical lpc2292/01 i dd(act) measured at different frequencies 002aad102 0 10 20 30 40 50 12 20 28 36 44 52 60 frequency (mhz) i dd(act) (ma) all peripherals disabled all peripherals enabled test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb = 25 c; core voltage 1.8 v; all peripherals enabled but not active. fig 7. typical lpc2292/01 i dd(act) measured at different voltages 002aad103 1.65 1.80 1.95 60 mhz 48 mhz 12 mhz 0 10 20 30 40 50 voltage (v) i dd(act) (ma)
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 36 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: active mode entered executing code on-chip ?ash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 8. typical lpc2292/01 i dd(act) measured at different temperatures 002aad104 5 15 25 35 45 -40 -15 10 35 60 85 12 mhz 48 mhz 60 mhz temperature ( c) i dd(act) (ma) test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb = 25 c; core voltage 1.8 v. fig 9. typical lpc2292/01 i dd(idle) measured at different frequencies 002aad105 0.0 2.0 4.0 6.0 8.0 10.0 12 20 28 36 44 52 60 frequency (mhz) i dd(idle) (ma) all peripherals disabled all peripherals enabled
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 37 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb =25 c; core voltage 1.8 v; all peripherals enabled but not active. fig 10. typical lpc2292/01 i dd(idle) measured at different voltages 002aad106 2.0 4.0 6.0 8.0 10.0 1.65 1.80 1.95 voltage (v) i dd(idle) (ma) 12 mhz 48 mhz 60 mhz test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 11. typical lpc2292/01 i dd(idle) measured at different temperatures 002aad107 -40 -15 10 35 60 85 12 mhz 48 mhz 60 mhz 1.0 2.0 3.0 4.0 5.0 6.0 temperature ( c) i dd(idle) (ma)
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 38 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: power-down mode entered executing code from on-chip ?ash. fig 12. typical lpc2292/01 core power-down current i dd(pd) measured at different temperatures 0 40 80 120 160 200 1.65 v 1.8 v 1.95 v 002aad108 -40 -15 10 35 60 85 temperature ( c) i dd(pd) ( m a) test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb =25 c; core voltage 1.8 v. fig 13. typical lpc2294/01 i dd(act) measured at different frequencies 002aad109 0.0 10.0 20.0 30.0 40.0 50.0 12 20 28 36 44 52 60 frequency (mhz) i dd(act) (ma) all peripherals enabled all peripherals disabled
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 39 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb = 25 c; core voltage 1.8 v; all peripherals enabled but not active. fig 14. typical lpc2294/01 i dd(act) measured at different voltages 002aad110 1.65 1.80 1.95 12 mhz 48 mhz 60 mhz 5.0 15.0 25.0 35.0 45.0 55.0 voltage (v) i dd(act) (ma) test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 15. typical lpc2294/01 i dd(act) measured at different temperatures 002aad111 -40 -25 -10 5 20 35 50 65 80 95 110 125 12 mhz 48 mhz 60 mhz 5.0 15.0 25.0 35.0 45.0 temperature ( c) i dd(act) (ma)
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 40 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb =25 c; core voltage 1.8 v. fig 16. typical lpc2294/01 i dd(idle) measured at different frequencies 002aad112 0.0 5.0 10.0 15.0 12 20 28 36 44 52 60 frequency (mhz) all peripherals disabled all peripherals enabled i dd(idle) (ma) test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; t amb =25 c; core voltage 1.8 v; all peripherals enabled but not active. fig 17. typical lpc2294/01 i dd(idle) measured at different voltages 002aad113 1.65 1.80 1.95 12 mhz 48 mhz 60 mhz 0.0 5.0 10.0 15.0 voltage (v) i dd(idle) (ma)
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 41 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 18. typical lpc2294/01 i dd(idle) measured at different temperatures 002aad114 -40 -25 -10 5 20 35 50 65 80 95 110 125 12 mhz 48 mhz 60 mhz 0.50 1.50 2.50 3.50 4.50 5.50 6.50 temperature ( c) i dd(idle) (ma) test conditions: power-down mode entered executing code from on-chip ?ash. fig 19. typical lpc2294/01 core power-down current i dd(pd) measured at different temperatures 0 100 200 300 400 500 1.65 v 1.8 v 1.95 v 002aad115 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( c) i dd(pd) ( m a)
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 42 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface test conditions: active mode entered executing code from on-chip ?ash; pclk = cclk 4 ; temp = 25 c; core voltage 1.8 v; all peripherals disabled. fig 20. typical lpc2292/01 and lpc2294/01 i dd(act) measured at different voltages 002aad116 1.65 1.80 1.95 12 mhz 48 mhz 60 mhz 5.0 15.0 25.0 35.0 45.0 voltage (v) i dd(act) (ma) test conditions: idle mode entered executing code from on-chip ?ash; pclk = cclk 4 ; temp = 25 c; core voltage 1.8 v; all peripherals disabled. fig 21. typical lpc2292/01 and lpc2294/01 i dd(idle) measured at different voltages 002aad117 1.65 1.80 1.95 12 mhz 48 mhz 60 mhz 0.0 5.0 10.0 voltage (v) i dd(idle) (ma) table 9. typical lpc2292/01 peripheral power consumption in active mode core voltage 1.8 v; t amb =25 c; all measurements in m a; pclk = cclk 4 ; all peripherals enabled. peripheral cclk = 12 mhz cclk = 48 mhz cclk = 60 mhz timer0 43 141 184 timer1 46 150 180 uart0 98 320 398 uart1 103 351 421
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 43 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 9. dynamic characteristics pwm0 103 341 407 i 2 c-bus 9 37 53 spi0/1 6 27 29 rtc165578 pcemc 306 994 1205 adc 33 128 167 can1/2 229 771 914 table 10. typical lpc2294/01 peripheral power consumption in active mode core voltage 1.8 v; t amb =25 c; all measurements in m a; pclk = cclk 4 ; all peripherals enabled. peripheral cclk = 12 mhz cclk = 48 mhz cclk = 60 mhz timer0 43 141 184 timer1 46 150 180 uart0 98 320 398 uart1 103 351 421 pwm0 103 341 407 i 2 c-bus 9 37 53 spi0/1 6 27 29 rtc165578 pcemc 306 994 1205 adc 33 128 167 can1/2/3/4 230 769 912 table 9. typical lpc2292/01 peripheral power consumption in active mode continued core voltage 1.8 v; t amb =25 c; all measurements in m a; pclk = cclk 4 ; all peripherals enabled. peripheral cclk = 12 mhz cclk = 48 mhz cclk = 60 mhz table 11. dynamic characteristics t amb = - 40 c to +125 c; v dd(1v8) , v dd(3v3) over speci?ed ranges. [1] symbol parameter conditions min typ max unit external clock f osc oscillator frequency supplied by an external oscillator (signal generator) 1 - 50 mhz external clock frequency supplied by an external crystal oscillator 1 - 30 mhz external clock frequency if on-chip pll is used 10 - 25 mhz external clock frequency if on-chip bootloader is used for initial code download 10 - 25 mhz t cy(clk) clock cycle time 20 - 1000 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 44 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] bus capacitance c b in pf, from 10 pf to 400 pf. t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (except p0[2] and p0[3]) t r rise time - 10 - ns t f fall time - 10 - ns i 2 c-bus pins (p0[2] and p0[3]) t f fall time v ih to v il [2] 20 + 0.1 c b --ns table 11. dynamic characteristics continued t amb = - 40 c to +125 c; v dd(1v8) , v dd(3v3) over speci?ed ranges. [1] symbol parameter conditions min typ max unit
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 45 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface table 12. external memory interface dynamic characteristics c l =25pf, t amb =40 c symbol parameter conditions min typ max unit common to read and write cycles t chav xclk high to address valid time - - 10 ns t chcsl xclk high to cs low time - - 10 ns t chcsh xclk high to cs high time - - 10 ns t chanv xclk high to address invalid time - - 10 ns read cycle parameters t cslav cs low to address valid time [1] - 5 - +10 ns t oelav oe low to address valid time [1] - 5 - +10 ns t csloel cs low to oe low time - 5 - +5 ns t am memory access time [2] [3] (t cy(cclk) (2 + wst1)) + ( - 20) -- ns t am(ibr) memory access time (initial burst-rom) [2] [3] (t cy(cclk) (2 + wst1)) + ( - 20) -- ns t am(sbr) memory access time (subsequent burst-rom) [2] [4] t cy(cclk) +( - 20) - - ns t h(d) data hold time [5] 0--ns t cshoeh cs high to oe high time - 5 - +5 ns t oehanv oe high to address invalid time - 5 - +5 ns t choel xclk high to oe low time - 5 - +5 ns t choeh xclk high to oe high time - 5 - +5 ns write cycle parameters t avcsl address valid to cs low time [1] t cy(cclk) - 10 - - ns t csldv cs low to data valid time - 5 - +5 ns t cslwel cs low to we low time - 5 - +5 ns t cslblsl cs low to bls low time - 5 - +5 ns t weldv we low to data valid time - 5 - +5 ns t csldv cs low to data valid time - 5 - +5 ns t welweh we low to we high time [2] t cy(cclk) (1 + wst2) - 5- t cy(cclk) (1 + wst2) + 5 ns t blslblsh bls low to bls high time [2] t cy(cclk) (1 + wst2) - 5- t cy(cclk) (1 + wst2) + 5 ns t wehanv we high to address invalid time [2] t cy(cclk) - 5-t cy(cclk) +5 ns t wehdnv we high to data invalid time [2] (2 t cy(cclk) ) - 5 - (2 t cy(cclk) )+5 ns t blshanv bls high to address invalid time [2] t cy(cclk) - 5-t cy(cclk) +5 ns
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 46 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface [1] except on initial access, in which case the address is set up t cy(cclk) earlier. [2] t cy(cclk) = 1 cclk . [3] latest of address valid, cs low, oe low to data valid. [4] address valid to data valid. [5] earliest of cs high, oe high, address change to data invalid. [1] see the lpc2119/2129/2194/2292/2294 user manual for a description of the wstn bits. t blshdnv bls high to data invalid time [2] (2 t cy(cclk) ) - 5 - (2 t cy(cclk) )+5 ns t chdv xclk high to data valid time - - 10 ns t chwel xclk high to we low time - - 10 ns t chblsl xclk high to bls low time - - 10 ns t chweh xclk high to we high time - - 10 ns t chblsh xclk high to bls high time - - 10 ns t chdnv xclk high to data invalid time - - 10 ns table 12. external memory interface dynamic characteristics continued c l =25pf, t amb =40 c symbol parameter conditions min typ max unit table 13. standard read access speci?cations access cycle max frequency wst [1] setting wst 3 0; round up to integer memory access time requirement standard read standard write burst read - initial burst read - subsequent 3 n/a f max 2 wst1 + t ram 20 ns + -------------------------------- wst1 t ram 20 ns + t cy cclk () -------------------------------- 3 2 C t ram t cy cclk () 2 wst1 + () 20 ns C f max 1wst2 + t write 5ns + ---------------------------------- wst2 t write t cyc 5 + C t cy cclk () ------------------------------------------- - 3 t write t cy cclk () 1 wst2 + () 5ns C f max 2 wst1 + t init 20 ns + -------------------------------- w st1 t init 20 ns + t cy cclk () -------------------------------- 3 2 C t init t cy cclk () 2 wst1 + () 20 ns C f max 1 t rom 20 ns + -------------------------------- - t rom t cy cclk () 20 ns C
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 47 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 9.1 timing fig 22. external memory read access xclk cs addr data oe t cslav t oelav t csloel t am t h(d) t cshoeh t oehanv t choeh t choel 002aaa749 fig 23. external memory write access xclk cs addr data bls/we oe t cslwel t cslblsl t weldv t csldv t welweh t blslblsh t wehanv t blshanv t wehdnv t blshdnv 002aaa750 t csldv t avcsl
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 48 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface fig 24. external clock timing t chcl t clcx t chcx t cy(clk) t clch 002aaa907 0.2v dd + 0.9 v 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 49 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 10. package outline fig 25. package outline sot486-1 (lqfp144) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.08 0.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 50 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface fig 26. package outline sot569-1 (tfbga144) 0.8 a 1 e 1 b a 2 unit d y e references outline version european projection issue date 03-07-09 05-09-14 iec jedec jeita mm 1.2 0.36 0.24 0.84 0.74 12.2 11.8 d 1 11.9 11.7 y 1 12.2 11.8 11.9 11.7 e 1 9.6 e 2 9.6 0.53 0.43 0.1 0.1 dimensions (mm are the original dimensions) sot569-1 mo-216 e 0.15 v 0.08 w 0 5 10 mm scale sot569-1 tfbga144: plastic thin fine-pitch ball grid array package; 144 balls; body 12 x 12 x 0.8 mm a max. a a 2 a 1 detail x x e 1 d d 1 e b a ball a1 index area y y 1 c c a c c b e e e 1 a c b e d g j l f h k n m 246810 13 12 1357911 e 2 ball a1 index area b ? v m ? w m shape optional (4 )
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 51 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 11. abbreviations table 14. acronym list acronym description adc analog-to-digital converter amba advanced microcontroller bus architecture apb advanced peripheral bus can controller area network cisc complex instruction set computer fifo first in, first out gpio general purpose input/output i/o input/output jtag joint test action group pll phase-locked loop pwm pulse width modulator risc reduced instruction set computer spi serial peripheral interface sram static random access memory ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 52 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 12. revision history table 15. revision history document id release date data sheet status change notice supersedes lpc2292_2294_6 20071210 product data sheet - lpc2292_2294_5 modi?cations: ? type number lpc2292fbd144/01 has been added. ? type number lpc2292fet144/01 has been added. ? type number lpc2294hbd144/01 has been added. ? details introduced with /01 devices on new peripherals/features (fast i/o ports, ssp, crp) and enhancements to existing ones (uart0/1, timers, adc, and spi) added. ? power consumption measurements for lpc2292/2294/01 added. ? description of jtag pin tck has been updated. lpc2292_2294_5 20070215 product data sheet - lpc2292_2294_4 lpc2292_2294_4 20060711 product data sheet - lpc2292_2294_3 lpc2292_2294_3 20051101 product data sheet - lpc2292_2294-02 lpc2292_2294-02 20041223 product data - lpc2292_2294-01
lpc2292_2294_6 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 06 10 december 2007 53 of 54 nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 13.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 13.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 14. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors lpc2292/lpc2294 16/32-bit arm microcontrollers with external memory interface ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 10 december 2007 document identifier: lpc2292_2294_6 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 key features brought by lpc2292/2294/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 key features common for all devices . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 functional description . . . . . . . . . . . . . . . . . . 15 6.1 architectural overview. . . . . . . . . . . . . . . . . . . 15 6.2 on-chip ?ash program memory . . . . . . . . . . . 15 6.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 17 6.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 18 6.7 external memory controller. . . . . . . . . . . . . . . 18 6.8 general purpose parallel i/o (gpio) and fast i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.8.2 features added with the fast gpio set of registers available on lpc2292/2294/01 only 19 6.9 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9.2 adc features available in lpc2292/2294/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.10 can controllers and acceptance ?lter . . . . . . 20 6.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.11 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.11.2 uart features available in lpc2292/2294/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 20 6.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13 spi serial i/o controller. . . . . . . . . . . . . . . . . . 21 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.2 features available in lpc2292/2294/01 only . 21 6.14 ssp controller (lpc2292/94/01 only). . . . . . . 22 6.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.15 general purpose timers . . . . . . . . . . . . . . . . . 22 6.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.15.2 features available in lpc2292/2294/01 only . 23 6.16 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23 6.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.17 real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 23 6.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18 pulse width modulator . . . . . . . . . . . . . . . . . . 24 6.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.19 system control . . . . . . . . . . . . . . . . . . . . . . . . 25 6.19.1 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 25 6.19.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.19.3 reset and wake-up timer . . . . . . . . . . . . . . . . 25 6.19.4 code security (code read protection - crp) 26 6.19.5 external interrupt inputs . . . . . . . . . . . . . . . . . 26 6.19.6 memory mapping control . . . . . . . . . . . . . . . . 26 6.19.7 power control . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.19.8 apb bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.20 emulation and debugging. . . . . . . . . . . . . . . . 27 6.20.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 27 6.20.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 28 6.20.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29 8 static characteristics . . . . . . . . . . . . . . . . . . . 30 8.1 power consumption measurements for lpc2292/01 and lpc2294/01 . . . . . . . . . . . . 35 9 dynamic characteristics . . . . . . . . . . . . . . . . . 43 9.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 49 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 52 13 legal information . . . . . . . . . . . . . . . . . . . . . . 53 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 53 13.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14 contact information . . . . . . . . . . . . . . . . . . . . 53 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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